In a conventional CMOS processes, the same spacer structure generally including a sidewall and optional offset spacer on the gate sidewalls is used to form all transistors in the integrated circuit. Although a single spacer structure simplifies the process flow, a conventional single spacer process does not provide flexibility with respect to the application/function for a given transistor (e.g. high voltage or speed), nor the type of transistor (e.g. PMOS or NMOS).
For example, NMOS and PMOS transistors may require different offset spacer widths for transistor performance optimization. Moreover, depending on application/function of a specific transistor in the circuit, it may provide better performance having a relatively thin or a relatively thick (wider) offset spacer. For example, regarding static random access memory (SRAM) devices, transistors used in the bit cells of the SRAM may require a thicker offset spacer compared to other transistors in the circuit to realize (i) a larger LEFFECTIVE, (ii) reduced impact on gate (poly) edge roughness (generally referred to as Line Edge Roughness, LER), and (iii) a reduced amount of pocket dopant penetrating through bottom of the offset spacer (or through poly edge in absence of an offset spacer). Items (i)-(iii) are known to impact SRAM bit cell transistor mismatch (local variation) which can degrade SRAM bit cell stability.
Although unconventional, process flows which use a thick offset spacer to form some devices and a thin offset spacer to form other devices, referred to as differential spacer processes, are known. In such a flow, following a conventional poly gate etch similar to a conventional offset spacer flow, the type of transistor that can be optimized better with thinner/no spacer (e.g. NMOS) is patterned, and the other transistors (e.g. PMOS) are covered with a making material such as photoresist. The patterned regions are implanted, followed by ashing the photoresist and cleaning. A thin layer of oxide is then generally formed or deposited and the required thickness of nitride offset spacer is deposited. Plasma etching of the nitride offset spacer layer is used to form the offset spacer structure for type of transistor that can be optimized better with thicker offset spacer (e.g. PMOS). The patterned regions are implanted followed by ashing the photoresist and cleaning. The conventional sequence of damage anneal, followed by source/drain (S/D) spacer deposition/patterning/implants, and other conventional steps are used to complete the formation of the integrated circuit.
Such a differential spacer process requires an additional oxide (buffer) layer be formed prior to depositing the nitride spacer layer to reduce the chance that the plasma nitride offset spacer etches doped silicon for other transistor type. Non-uniformity in underlying/remaining oxide thickness can cause significant variability in transistors formed post offset spacer etch. Moreover, such a differential spacer flow requires a deeper medium doped drain (MDD) extension implant to ensure that a significant portion of the MDD implant dose gets into the silicon and does not instead end up in the buffer oxide layer.